1. Field of the Invention
The present invention relates to switching DC-to-DC converters having multiple power channels (either simple-paralleled or interleaved-paralleled) and multiple control signal channels, in which the duty cycle of each power channel is controlled by one of the control signal channels. Specifically, the invention employs rotation of a set of control signal channels (relative to a set of power channels) to reduce the differences between the time-averaged currents through the individual power channels.
2. Description of the Related Art
One type of conventional switching power supply circuitry which employs voltage mode control to achieve output voltage regulation is a DC-to-DC converter including a voltage mode switching controller chip, and circuitry external to the controller chip which defines multiple, paralleled power channels. The controller chip includes multiple control signal channels (one for each power channel), each control signal channel generating a pulse width modulated power switch control signal ("PWM switch control" signal) in response to a ramped voltage and a feedback signal indicative of the DC-to-DC converter's output potential. Typically, each PWM switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signal. Typically, the ramped voltage signals for all the channels increase periodically (with the same period for all channels) at a fixed ramp rate, and their waveforms are identical (to the extent possible and practical), except that each may have a different phase than the others. In interleaved PWM DC-to-DC converters, the ramped voltage signals and PWM switch control signals are out of phase with respect to each other. In non-interleaved PWM DC-to-DC converters having multiple channels, the ramped voltage signals and PWM switch control signals are in phase with respect to each other.
Each PWM switch control signal controls the power switch of a different one of the parallel power channels. For example, in PWM DC-to-DC converters, multiple PWM switch control signals are generated (in parallel) by providing multiple ramped voltages in parallel to comparator circuitry. Typically, it is desired that the PWM switch control signals all have the same duty cycle. Often, the PWM switch control signals are generated in a voltage mode switching controller chip, and asserted to external power switch circuitry (comprising multiple power switches) to cause the latter circuitry to determine the amplitude of the DC output voltage of the DC-to-DC converter. An advantage of providing multiple channels (each channel including a power switch) rather than a single channel is that use of multiple channels allows the DC-to-DC converter to be implemented with smaller power stage inductors, smaller input filter inductors, and smaller output capacitors, thus providing an overall improved step-load transient response and reduced physical size.
However, when implementing a multi-channel switching controller (especially when implementing it as an integrated circuit or part of an integrated circuit), process and temperature variations typically cause variations in the characteristics (e.g., maximum amplitude) of the ramped voltages generated in the individual control signal channels. Such variations typically cause or contribute to undesired variation from power channel to power channel in the time-averaged duty cycle of each power switch, and in the time-averaged current drawn from each power channel. This problem is sometimes referred to as "current hogging" by one or more power channels, or as the "hot channel" problem. When implementing a multi-channel DC-to-DC converter, a variety of factors typically contribute to the hot channel problem, including mismatches among the external power switches or other elements of the power channel circuitry external to the controller, as well as variations (from control signal channel to control signal channel) in implementation of the controller.
When implementing a multi-channel DC-to-DC converter, it is desirable to reduce or eliminate the hot channel problem, thus reducing mismatches causing any of the power channels from drawing significantly time-averaged current than any of the other power channels. Preferably, the converter is implemented so that all the power channels draw at least approximately the same time-averaged current.
FIG. 1 is a simplified circuit diagram of a conventional DC-to-DC converter which employs feedback of a type known as voltage-mode feedback which exhibits the "hot" channel problem in DC-to-DC converters having multiple (parallel) power channels. Specifically, mismatches in the slopes of ramped voltage V.sub.osc output from oscillator 2 for each channel of controller chip 1, can result in mismatches in the current conducted through the inductor L, switch N1 and diode D for each channel of the circuit. The degree of mismatch depends on the ramp rate of voltage V.sub.osc, the particular implementation of oscillator 2 and comparator 8, as well as other circuitry within and external to controller chip 1. Thus, in a multi-channel implementation of the FIG. 1 circuit including comparators (such as comparator 8) and circuitry for generating ramped voltages (such as voltage V.sub.osc) within each control signal channel, differences in V.sub.osc, inductor value, switch resistance and diode forward voltage can cause the "hot" channel problem by inducing variations (from power channel to power channel) in the time-averaged duty cycles of the power switches.
The FIG. 1 circuit includes voltage mode switching controller 1 (implemented as an integrated circuit) and buck converter circuitry external to controller chip 1. The buck converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, Schottky diode D, capacitor C.sub.out feedback resistor divider R.sub.F1 and R.sub.F2, compensation resistor R.sub.c, and compensation capacitor C.sub.c, connected as shown. The FIG. 1 circuit produces a regulated DC output voltage V.sub.out across load R.sub.o, in response to input DC voltage V.sub.in.
Controller chip 1 includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an output potential V.sub.DR at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having "set" terminal coupled to oscillator 2, "reset" terminal coupled to the output of comparator 8 (having a first input coupled to the second output of oscillator 2 and a second input coupled to pad 13 and the output of error amplifier 10, and an output coupled to the input of driver 6), error amplifier 10 (having a non-inverting input maintained at reference potential V.sub.ref), digital-to-analog conversion circuit 10A (which maintains the noninverting input of amplifier 10 at analog reference potential V.sub.ref, in response to digital control bits VIDCODE which determine the reference potential V.sub.ref and which are received from an external source at one or more pads 16).
Pad 13 of controller chip 1 is at potential V.sub.c, which is determined by the output of error amplifier 10 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V.sub.ref) and the values of external resistor R.sub.c and capacitor C.sub.c, connected to pad 13 as shown. Reference potential V.sub.ref is set in response to bits VIDCODE and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V.sub.out, resistors R.sub.F1 and R.sub.F2 with the appropriate resistance ratio R.sub.F1 /R.sub.F2 are employed.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading edge of this pulse train sets latch 4. Each time latch 4 is set, the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 causes transistor N1 to turn on, which in turn causes current I.sub.L from the source of N1 to increase in ramped fashion (more specifically, the current I.sub.L increases as a ramp when transistor N1 is on, and is zero when transistor N1 is off. The current through diode D is zero when N1 is on, it increases sharply when N1 switches from on to off, then falls as a ramp while N1 is off, and then decreases sharply to zero when N1 switches from off to on). Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential R.sub.ref and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train.
Oscillator 2 asserts ramped voltage V.sub.osc (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. The ramped voltage is asserted to the non-inverting input of comparator 8.
Error amplifier 10 asserts the potential V.sub.c to the inverting input of comparator 8. When V.sub.c =V.sub.osc (after latch 4 has been set), the output of comparator 8 resets latch 4, which in turn causes the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by the described use of both of the signals output from oscillator 2, and feedback asserted to error amplifier 10 from Node A, controller chip I switches transistor N1 on and off with timing that regulates the output potential V.sub.out of the FIG. 1 circuit.
FIG. 1A is a simplified circuit diagram of a conventional DC-to-DC converter which employs feedback of a type called current-mode feedback which can be used to address the "hot" channel problem in DC-to-DC converters having multiple (parallel) power channels. Specifically, the feedback provided through pads 14 and 14A to controller chip 1 of FIG. 1A provides a ramped voltage V.sub.s which is compared with the feedback signal indicative of the DC-to-DC converter's potential(allowing control of the time-averaged duty cycle of external power switch N1). The value and slope of V.sub.s depends on the current through inductor L (and thus through resistor R.sub.s), current sense amplifier 11, and the potentials at the converter's input and output and the potentials at other circuit elements within and external to controller chip 1A. The voltage V.sub.osc adjusts the effective ramp rate slightly for improved stability through a technique called "slope compensation." The adjusted feedback signal V.sub.c -V.sub.osc controls the peak value the inductor is allowed to ramp up to through the external power switch N1, as indicated by the current feedback signal V.sub.s. Thus, in a multi-channel implementation of the FIG. 1A circuit including a comparator (such as comparator 8) and current feedback circuitry for generating a ramped voltage (such as voltage V.sub.s) within each control signal channel and at least one pad (such as pads 14 and 14A) for feedback from each power channel to each control signal channel, use of a single feedback signal V.sub.c to set the same peak switch current in each power channel can address the "hot" channel problem by causing the controller to set the same time-averaged current through all the power switches.
The FIG. 1A circuit includes current mode switching controller 1A (implemented as an integrated circuit) and buck converter circuitry external to controller chip 1A. The buck converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor R.sub.s, Schottky diode D, capacitor C.sub.out, feedback resistor divider R.sub.F1, and R.sub.F2, compensation resistor R.sub.c, and compensation capacitor C.sub.c, connected as shown. The FIG. 1A circuit produces a regulated DC output voltage V.sub.out across load R.sub.o, in response to input DC voltage V.sub.in.
Controller chip 1A includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an output potential V.sub.DR at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having "set" terminal coupled to oscillator 2, "reset" terminal coupled to the output of comparator 8, and an output coupled to the input of driver 6), error amplifier 10 (having a non-inverting input maintained at reference potential V.sub.ref), digital-to-analog conversion circuit 10A (which maintains the noninverting input of amplifier 10 at analog reference potential V.sub.ref, in response to digital control bits VIDCODE which determine the reference potential V.sub.ref and which are received from an external source at one or more pads 16), circuit 9 (having a first input coupled to the second output of oscillator 2, a second input coupled to pad 13, and an output coupled to the inverting input of comparator 8), and current sense amplifier 11 (having a non-inverting input coupled through pad 14 to the node between inductor L and resistor R.sub.s, an inverting input coupled through pad 14A to the buck converter circuitry's output node, and an output coupled to the non-inverting input of comparator 8).
Pad 13 of controller chip 1A is at potential V.sub.c, which is determined by the output of error amplifier 10 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V.sub.ref) and the values of external resistor R.sub.c and capacitor C.sub.c, connected to pad 13 as shown. Reference potential V.sub.ref is set in response to bits VIDCODE and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V.sub.out, resistors R.sub.F1 and R.sub.F2 with the appropriate resistance ratio R.sub.F1 /R.sub.F2 are employed.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading edge of this pulse train sets latch 4. Each time latch 4 is set, the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 causes transistor N1 to turn on, which in turn causes current I.sub.L from the source of N1 to increase in ramped fashion (more specifically, the current I.sub.L increases as a ramp when transistor N1 is on, and is zero when transistor N1 is off. The current through diode D is zero when N1 is on, it increases sharply when N1 switches from on to off, then falls as a ramp while N1 is off, and then decreases sharply to zero when N1 switches from off to on). Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential R.sub.ref and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train.
Oscillator 2 optionally also asserts ramped voltage V.sub.osc (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. Circuit 9 asserts the potential V.sub.c -V.sub.osc (or V.sub.c) to the inverting input of comparator 8.
The non-inverting input of comparator 8 is at potential V.sub.s =I.sub.L R.sub.s, which is the output of current sense amplifier 11, and which increases in ramped fashion in response to each "set" of latch 4 by oscillator 2. When V.sub.s =V.sub.c -V.sub.osc (or V.sub.s =V.sub.c) after latch 4 has been set, the output of comparator 8 resets latch 4, which in turn causes the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by the described use of all of the signals output from oscillator 2, current feedback to current sense amplifier 11, and feedback asserted to error amplifier 10 from Node A (through pad 15), controller chip 1A switches transistor N1 on and off with timing that regulates the output potential V.sub.out of the FIG. 1A circuit.
In a multi-channel implementation of FIG. 1A, the feedback through pads 14 and 14A of FIG. 1A (and counterparts thereto which are connected to the other power channels) could address the "hot channel" problem. In such multi-channel implementation, the controller would have only a single external pin (at pad 15) for feedback indicative of the output node (there would be one comparator for each control signal channel and the output of a single error amplifier 10 would be coupled to all comparators) but would have several external pins, each pair of external pins corresponding to pads 14 and 14A, each coupled to a different one of the power channels. Although the feedback from each power channel to a corresponding control signal channel could address the hot channel problem by reducing variations (from power channel to power channel) in the time-averaged power switch duty cycles and time-averaged currents drawn from the individual power channels, the feedback technique has the disadvantages that it requires a complex controller design with multiple external pins (two for each power channel) dedicated to addressing the hot channel problem, and requires current sense resistors such as resistor R.sub.s (one for each power channel) for generating the required feedback signals for addressing the hot channel problem.
Other techniques have been proposed for addressing the hot channel problem. For example, U.S. patent application No. 09/231,046, filed Jan. 14, 1999 and assigned to the assignee of the present invention, discloses ramped voltage generation circuitry for use in a switching controller for a DC-to-DC converter having multiple power channels. The ramped voltage generation circuitry generates multiple ramped voltages, each having a different phase. The maximum amplitude of each ramped voltage is controlled in the following manner to be uniform. In response to a clock signal (one clock signal per control signal channel), ramped voltage generating capacitors (one or two per control signal channel) are periodically charged and discharged. For each control signal channel, a feedback loop (comprising an amplifier, capacitor, transistor, and current mirror) controls the rate at which the ramped voltage generating capacitor (for the relevant control signal channel) charges, using feedback (provided during a short interval of time immediately before the ramped voltage generating capacitor discharges) indicative of the voltage across the ramped voltage generating capacitor. Although each ramped voltage generating capacitor charges periodically and discharges periodically, the feedback tends to move the level of each ramped voltage signal toward a desired maximum amplitude (during the short interval of time just before the ramped voltage generating capacitor discharges). However, this system addresses the hot channel problem in a manner requiring complex feedback circuitry within ramped voltage generation circuitry in the controller chip.
U.S. Pat. No. 5,959,441, issued Sep. 28, 1999 (assigned to Dell USA, L.P.), discloses another technique for addressing the hot channel problem. This technique employs a voltage mode control circuit, including amplifier 220 of FIG. 2A, a first integrator (comprising elements 241 and 223 of FIG. 2A), and a second integrator (comprising elements 238 and 235), which responds to feedback from each switch control channel to reduce the difference between the time-averaged duty cycles of the power channels. However, the system of U.S. Pat. No. 5,959,441 addresses the hot channel problem in a manner requiring complex feedback circuitry within the control signal channels.
Another technique proposed for addressing the hot channel problem is the technique of current sharing between the control signal channels (whether the paralleled power switch control signals are interleaved or non-interleaved). To implement current sharing, current sharing circuitry generates individual power channel current signals (indicative of the current drawn from each power channel), an average current signal (indicative of the average of the currents drawn from the power channels), and channel current error signals (indicative of the difference between the individual power channel current drawn from each power channel and the average current drawn from all power channels. Each power switch control signal (one for each power channel) is generated in response to two feedback signals: the current error signal (for the appropriate channel) and a second feedback signal indicative of the output potential of the DC-to-DC converter relative to a reference potential. Thus, the DC-to-DC converter achieves a desired output potential with increased current sharing among the channels (reduced differences between the time-averaged currents drawn by the individual power channels). However, the current sharing technique for addressing the hot channel problem has disadvantages, including that it requires controller chip pins dedicated to receiving feedback from the individual power channels (in order to implement current sharing), and it requires feedback circuitry within the controller chip for generating the current error signals (one for each control signal channel) and employing the current error signals as feedback.
Designing a multi-channel DC-to-DC converter in accordance with the present invention reduces the hot channel problem while eliminating the need for feedback from individual power channels or complex feedback circuitry within the individual control signal channels of the controller chip.
Some conventional multi-channel DC-to-DC converters include a switching controller chip, and power channel circuitry (e.g., boost converter circuitry) other than buck converter circuitry external to the controller chip. Some conventional multi-channel DC-to-DC converters employ switching controllers which receive only feedback indicative of the potential at the converter's output node (such as the feedback supplied to controller 1 of FIG. 1 from Node A of FIG. 1), and do not receive feedback indicative of the current through the inductor of each individual power channel (e.g. the feedback supplied through pads 14 and 14A of FIG. 1A). Another conventional multichannel DC-to-DC converter includes a switching regulator chip (which performs the functions of a switching controller and also includes internal power switches), and additional circuitry external to the regulator chip (in contrast with a converter that includes a controller chip having internal control signal channel circuitry, and external power channel circuitry outside the controller chip). It is contemplated that all such conventional converters can be improved in accordance with the invention.